1. Field of the Invention
This invention relates generally to a digital signal processing circuit and more particularly is directed to a digital signal processing circuit in which the processing speed is lowered.
2. Description of the Prior Art
In the existing digital signal processing circuit, particularly the digital adder circuit in which at least two input digital signals are added together, a so-called fast carry type full adder system is used. This type of adder system is suitable for handling the digital signal with the small number of bits and the high frequency clock rate because this type of adder system is very high in processing speed, but this type of adder system can not be applied to a circuit for handling the digital signal with the large number of bits, for example, 8-bit digital signal because the number of the circuit elements is exponentially increased with the increase of the number of bits. Another type of adder system is a so-called ripple carry type full adder system in which a plurality of full adders, each of which is suitable for handling the relatively small bits, is operated time sequentially. Therefore, in this type of adder system, each full adder must be operated at a relatively fast speed when the clock frequency is high. So, the circuit element or base logic forming each of the full adders must be a high speed logic element, such as transistor-transistor logic (TTL) or emitter-coupled-logic (ECL) which are not suitable for increasing the integrating density and for decreasing the power consumption. And, the logic element, such as complementary metal oxide semiconductor (CMOS) which is a relatively low speed logic but suitable for increasing the integrating density and for decreasing the power consumption can not be applied, too.
Recently, it has been proposed that the signal processing circuit for a color signal encoder is made in a digital fashion. In such a digital encoder, the sampling frequency that is the clock frequency, must be selected fairly high, such as 3fsc or 4fsc, where fsc is the frequency of the subcarrier, to increase the resolution of the video signal and to decrease the aliasing distortions and the number of bits must be selected large enough to obtain the sufficient gradation of the picture. But, the large part of the digital color encoder is formed of the digital adder circuits, for example, a matrix circuit, a Y/C mixing circuit etc. Therefore, in the digital color encoder, it is very difficult to use the above mentioned type of adder system.